The invention relates generally to the testing of integrated circuits, and more particularly, to methods and apparatuses for testing the input/output characteristics of an integrated circuit.
Integrated circuits such as, for example, Application Specific Integrated Circuits (i.e., ASICs), are constantly evolving with advances in functionality and performance. With increases in functionality and performance, there is a greater need than ever to test an integrated circuit for proper functionality. Of particular testing importance is whether the chip or die which is the integrated circuit is a known good die. However, advances in functionality and performance of integrated circuits has made it increasingly difficult to perform such tests.
One area of particular testing importance is the proper functionality of an integrated circuit""s input/output (i.e., I/O) circuitry. Specifically, for a known good die to be established, each I/O circuit must be tested for proper functionality before the known good die is embedded into a package. Accordingly, if the integrated circuit contains 256 I/O, each of the 256 I/O must be tested. Similarly, if the integrated circuit contains 512 I/O, each of the 512 I/O must be tested. Such testing is generally accomplished via testing equipment which includes a sufficient number of test elements for connection to each I/O. For example, to test an integrated circuit with 256 I/O, the test equipment would need at least 256 test elements, one test element for each I/O. However, if the integrated circuit to be tested includes 512 I/O, the same piece of test equipment may not have 512 test elements and, therefore, lacks capacity to test such an integrated circuit. Consequently, as the number of I/Os in an integrated circuit increases, the ability of existing test equipment to test such integrated circuits is limited by the number of test elements possessed by the testing equipment. Therefore a method of testing integrated circuits which does not particularly depend on the type of testing equipment is highly desirable.
The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test elements present on the testing device. This is accomplished by the present invention by providing a method for testing a chip having the steps of: providing a plurality of switches on the chip which are associated with a plurality of input/output circuits on the chip; selectively changing the state of a pre-determined number of the plurality of switches from a first state to a second state; applying a test condition to a predetermined number of the plurality of input/output circuits on the chip through the plurality of switches; applying a test condition to the predetermined number of the plurality of input/output circuits on the chip through the plurality of switches; and measuring a resultant condition from the predetermined number of input/output circuits to determine if any of the predetermined number of input/output circuits on the chip are faulty.
Various embodiments of the present invention are disclosed in the form of a plurality of test configurations which test specific operational features or components of the integrated circuit""s I/O circuitry. In this regard, the present invention discloses an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test.
The various I/O test configurations of the present invention are embodied in one or more of the following tests: an I/O Short-Circuit test configuration which verifies that each I/O is not short-circuited to a supply voltage or to ground; an I/O Negative and Positive Leakage test configuration; a Pull-Up and Pull-Down Resistor test configuration; Differential I/O test configuration; a Package test configuration; an I/O Driver Least Positive Up Level (LPUL) and Most Positive Down Level (MPDL) test configuration; a single-ended I/O receiver LPUL and MPDL test configuration; a differential I/O receiver LPUL and MPDL test configuration; and Differential I/O Terminator Resistor Test configuration.
It is therefore an advantage of the present invention to provide a method of testing an integrated circuit""s I/O circuitry by using only a limited number of pins, regardless of the number of integrated circuit I/O circuitry required to be tested.
It is a further advantage of the present invention to provide a method of testing an integrated circuit""s I/O circuitry without all of the I/O circuitry being connected to the testing device.
It is still a further advantage of the present invention to provide an integrated circuit which can be tested through a limited number of external connections, regardless of the number of circuits required to be tested.